The present invention relates to an improved synchronizing circuit and more particularly to a synchronizing circuit for synchronizing a first clock signal to a second clock signal over a wide range of first clock signal frequencies and pulse widths.
There are many instances in modern electronic technology wherein it is necessary to synchronize a first clock signal to a second clock signal to derive a synchronized signal which is compatible with circuitry using the second clock signal. This function is performed by synchronizing circuits which find application in discrete circuits as well as integrated circuits. Preferably, the synchronizing circuit should be capable of synchronizing a first clock to a second clock which are completely asynchronous and frequency independent.
One problem often encountered by synchronizing circuits is that the first clock signal has a frequency which is out of the range of the synchronizing circuit. In such cases, the synchronizing circuit is incapable of synchronizing the first clock signal to the second clock signal or, at best, can accomplish synchronization by only providing a synchronized signal which is not uniform. Obviously, the lack of synchronization is not acceptable in any application wherein synchronization is required and a synchronized signal which is not uniform is also generally not acceptable in most applications.
Another problem often encountered is the component count of the synchronizing circuit. This problem is most often encountered when a synchronizing circuit is implemented within an integrated circuit since integrated die area is very important. Hence, there is a continued need for a synchronizing circuit which may be implemented with fewer components to decrease the integrated circuit die area required for this function.
The present invention overcomes the aforementioned problems by providing a synchronizing circuit which is capable of deriving a synchronized clock output from a first clock signal which is synchronized to a second clock signal wherein the first clock signal may very widely in frequency and pulse width as long as its frequency is not higher than the second clock signal frequency. The synchronizing circuit accomplishes this end, while also reducing the number of required components by including a set-reset latch and a delay circuit.